1绪论及工艺基础.ppt

* 从器件到电路：多层互连 * 从硅片到芯片：加工后端 * 从硅片到芯片：加工后端 * 从硅片到芯片：加工后端 * Jack won 2000 Noble prize because of this J-K Flipflop * TTL had a higher integration density than ECL Power – puts an upper limit on the number of gates that can be reliably integrated on a single die * PMOS came first because of fab problems with NMOS NMOS next because of fab problems with CMOS (NMOS has speed advantage over PMOS due to carrier mobility) * * average minimum channel length has a reduction rate of approx. 13% per year, halving every 5 years. No real sign of a slow-down in sight! Experimental .025 micron CMOS devices have been demonstrated in the laboratory and display current characteristics that are surprisingly close to present day transistors. * at 100nm, a PSM could cost $50,000; an EUV mask $40,000 to $60,000, and a SCALPEL $27,000 compared to $5K to $10 for a standard binary mask * 按比例CE规则对电路影响 综合考虑速度和功耗的参数PDP按3次方减小，而面积，按照平方减小 可见，CE规则变化的器件集成度按平方增加，速度线性增加，而功耗平方减小 这就是为什么人们不断追求半导体工艺的进步的主要原因 * 按比例变化CE α1 工艺参数的按比例缩小 器件尺寸（Tox，L，W，Xj） 1/α 掺杂浓度（Na，Nd） α 电源电压（Vdd） 1/α 器件参数的变化 电场 1 载流子速度 1 耗尽区宽度 1/α 电容 1/α 漂移电流 1/α 沟道电阻 1 电路参数的变化 电路的延迟(T~CV/I) 1/α 好 器件的功耗(P~VI) 1/α2 很好 功耗延迟乘积PDP(=PT) 1/α3 非常好 * 按比例缩小理论 恒定电场原则CE 恒定电压原则CV 准恒定电场原则QCE * Silicon’s Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180 130 100 70 50 35 Chip size (mm2) 170 214 235 269 308 354 Clock rate (GHz)* 1.2 1.6 2.2 2.8 3.6 4.4 Power supply Vdd (V) 1.8 1.5 1.2 0.9 0.7 0.6 Power (W) 90 130 160 170 174 183 For a Cost-Performance MPU (L1 on-chip SRAM cache; 32KB in 1999 doubling every two years) * Worldwide Semiconductor Revenue Source: ISSCC 2003 G. Moore “No exponential is forever, but ‘forever’ can be delayed” * 绪论 集成电路的历史 集成电路的发展规律 等比例缩小原则 未来发展和挑战 * Gate Length Scaling 微电子未来发展—more moore * 微电子未来发展—more than moore * * 微电子未来挑战：物理极限 1999 – 1000 electrons to change state 2010 – 8 electrons to change state 2020 - 1 electron to change state Source: California Computer News, 2003 * 微电子未来挑战：工艺技术 光刻线条 晶圆尺寸 * 微电子未