二《数字逻辑设计与应用》期中试卷参考解答.doc

电子科技大学2014 - 2015 学年第 二 学期期 中 考试卷 课程名称：数字逻辑设计及应用 考试形式：闭卷 考试日期：2015年5月10日 考试时长：120分钟 课程成绩构成：平时 30/20 %， 期中 30/20 %， 小班讨论 0/20 %， 期末 40 % 本试卷试题由__VII___部分构成，共__6___页。 题号 I II III IV V VI VII 合计 得分 I. Please fill out the correct answers in the brackets “( )” . ( 2’ X 20 = 40’ ) 1. [510.5] 10 = ( 111111110.1 )2 = ( 1FE.8 ) 16 2. (2015)10 =( 0010000000010101 )8421BCD =( 0101001101001000 ) Excess-3 3. If X’s signed-magnitude representation XSM is 000110102, then (2X)’s 8-bit two’s complement representation is ( ), and (-X/2)’s 8-bit two’s complement representation is (). 4. If a logic function is , its complement expression is (0,4,5,7), and its dual expression is.(0,2,3,7) 5. For CMOS inverters, can different outputs of common CMOS inverters be connected together? [Yes or No] ( No ); Three-state inverters have three-state outputs, which are HIGH、LOW and ( Hi-Z ). Can different outputs of three-state inverters be connected together? [Yes or No] ( Yes ). 6. Given a binary number X=101101012, its corresponding Gray code is (). 7. If [X] two’s-complement =0111 00112, [Y] two’s-complement =1001 11002, then [X-Y] two’s-complement=（），whether overflow occurs? [Yes or No] ( Yes ). 8. Given 126 different states, it requires at least ( 7 ) binary bits to represent them. 9. For CMOS NOR gates, their unused inputs should connect to ( 0 ) state. 10. From Table 1 below, if 74HC devices drive 74LS devices, in HIGH state , DC noise margin VNH is ( 1.84 ), Fan-out NH is ( 200 ); in LOW state , DC noise margin VNL is ( 0.47 ), Fan-out NL is ( 10 ). Table 1 Family Description Symbol 74LS 74HC LOW-level input voltage (V) VILmax 0.8 1.35 LOW-level output voltage (V) VOLmax 0.5 0.33 HIGH-level input voltage (V) VIHmin 2.0 3.85 HIGH-level output voltage (V) VOHmin 2.7 3.84 LOW-level input current (uA) IILmax -400 1 LOW-level output current