DDR验证和调试的高级方法.pdf

Validating and Debugging DDR2, DDR3 SDRAM Designs - Comprehensive Test solution from Analog to Digital Validation for All DDR Versions name title Memory Design and Validation Chip/Component Design Precise understanding of circuit behavior under range of conditions Margin testing System Integration Signal integrity and timing analysis, discovery of issues under nominal conditions Debug interoperability issues Embedded Systems Easy test setup Quick pass/fail results 2 2010-4-26 Tektronix Innovation Forum 2010 DDR Test Challenges Signal Access Probing – Easy-to-use / reliable connections – Bandwidth Signal Integrity – Affordable Isolation of Read/Write bursts – Triggering or Post-Processing Complexity of JEDEC Conformance Tests – Parametric timing/amplitude measurements – Vref / Vih / Vil, Derating Results Validity / Statistics Effective Reporting / Archiving Advanced Analysis – Characterization – Debug 3 2010-4-26 Tektronix Innovation Forum 2010 Fast Accurate instrument solutions DDR, DDR2 DDR3 SDRAM Solutions Signal Path Characterization and Analog Electrical Debug Digital Validation Debug SDRAM Probing Solutions Circuit Board Verification DSA Sampling Oscilloscopes DPO/DSA real time scopes TLA Logic Analyzers with Nexus software FuturePlus Technology memory supports Easy and reliable physical Verify correct design and Signal integrity measurements connection wi