7段译码电路设计.pptVIP

7段译码器设计 2012-2-13 内容提要 用并行语句设计 在进程语句中设计 用ROM设计 动态扫描译码器设计 硬件电路 用并行语句设计 级数多，运行速度慢 在进程语句中设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECL7S IS PORT( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); R: IN STD_LOGIC; LED7S: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END DECL7S; ARCHITECTURE ONE OF DECL7S IS BEGIN PROCESS(A,R) BEGIN IF R='1' THEN CASE A IS WHEN "0000" => LED7S<="1000000"; WHEN "0001" => LED7S<="1111001"; WHEN "0010" => LED7S<="0100100"; WHEN "0011" => LED7S<="0110000"; WHEN "0100" => LED7S<="0011001"; WHEN "0101" => LED7S<="0010010"; WHEN "0110" => LED7S<="0000010"; WHEN "0111" => LED7S<="1111000"; WHEN "1000" => LED7S<="0000000"; 只有一级，速度快 用ROM设计 编辑ROM文件 新建原理图 生成ROM模块 连线 不使用逻辑宏单元 动态扫描译码器设计 LED数码显示电路 从电路看，该数码显示器是共阴极结构 bcdin 输入的数据 bcdsel 位选信号 leddata 7段译码输出 ledsel 位选输出 实体定义 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bcd_led is port ( leddata: out std_logic_vector(7 downto 0); ledsel: out std_logic_vector(3 downto 0); bcdin : in std_logic_vector(3 downto 0); bcdsel: in std_logic_vector(1 downto 0) ); end bcd_led; 7段译码 architecture behave of bcd_led is signal bcdtmp: std_logic_vector(3 downto 0); signal bcdseltmp: std_logic_vector(1 downto 0); begin process(bcdsel) begin bcdtmp<=bcdin; bcdseltmp<=bcdsel; case bcdtmp is when "0000"=> leddata<=; when “0001”=> leddata<=; when "0010"=> leddata<=; when "0011"=> leddata<=; when "0100"=> leddata<=; when "0101"=> leddata<=; when "0110"=> leddata<=; when"0111"=> leddata<=; when"1000"=> leddata<=; when"1001"=> leddata<=; when"1010"=> leddata<=; when"1011"=> leddata<=; when"1100"=> leddata<=; when"1101"=> leddata<=; when"1110"=> leddata<="10011110