数字电路与逻辑设计教学 6.7 VerilogHDL在时序电路的设计.pdfVIP

2015/4/15 1 A Guide to Verilog HDL for Sequential Circuit 苏钢 gsu@hust.edu.cn 2015-04-11 Introductory information ?3’b101 width’base formatnumber ?parameter BIT=1, BYTE=8,PI=3.1415926; ?‘define (global) ?reg [3:0] Counter; ?reductions operator(缩位) e.g., A=4’b1010, ^A=A[0]^A[1]^A[2]^A[3]=1’b1;&A=0 ?Concatenation operators(位拼接) e.g., A=1’b1,C=2’b10, Y={A,C}=3’b110 2 Introductory information (cont.) module module_name(ports) ports declaration; parameter; data type definitions; behavior description endmodule 3 ?Blocking Assignment Statement 阻塞型赋值 = ?Non-Blocking Assignment Statement 非阻塞型赋值 <= e.g., A=2,B=4 begin begin B=A; B<=A; C=B+1; C<=B+1; end end Introductory information (cont.) C is 3 C is 5 4 Outline ?Behavior of flip-flops ?Behavior of shift registers ?Behavior of counters ?State machine ?Home work 5 Combinational-logic-circuit-based reg wire cl_a; assign cl_a = a ?A:B; 6 reg cl_a; always @(a or A or B) begin cl_a = a? A : B; end 2015/4/15 2 Flip-flop-based reg ? reg f_a; ? always @(posedge clk) ? begin f_a <= a ? A : B; end 7 Behavior of D Flip-flop module A_DFF (Q,D,CP,Rd); output Q; input D,CP,Rd; reg Q; always @(posedge CP or negedge Rd) if (~Rd) Q<=1’b0; else Q<=D; endmodule; //with asynchronous reset module S_DFF (Q,D,CP,Rd); output Q; input D,CP,Rd; reg Q; always @(posedge CP ) if (~Rd) Q<=1’b0; else Q<=D; endmodule; //with synchronous reset 8 Behavior of JK Flip-flop module JK_FF (J,K,CP,Q,Qn); output Q,Qn; input J,K,CP; reg Q; assign Qn=~Q; always @(negedge CP) case ({J,K}) 2’b00: Q<=Q; 2’b01: Q<=1’b0; 2’b10: Q<=1’b1; 2’b11: Q<=~Q; endcase; endmodule; 9 Behavior of universal shift registers ? Serial input / Serial output Shift register ? Universal Shift Register ? SN74LS194 – Parallel input / parallel output – Four Parallel data inputs permit parallel loading of external data. – Two serial input, one for left-shift, and the other for right-shift. – Serial output data are taken from either Q0(LSB) or Q3(MSB) depending on s